Digital - System Test And Testable Design: Using ...

The book by Zainalabedin Navabi (2010) is a comprehensive guide that bridges the gap between digital design and testing methodologies. Unlike traditional texts, it uses Verilog HDL to describe and simulate test hardware, making complex concepts like fault simulation and test generation more practical and less ambiguous for designers. Core Features and Methodology

A distinguishing feature is the extensive use of the Verilog Programming Language Interface (PLI) . This allows for a mixed hardware/software environment where users can develop "virtual testers" to evaluate complex test strategies.

This book is widely used as a primary text in and Design for Testability courses. More information can be found at Springer Nature or through retailers like Amazon . Digital System Test and Testable Design: Using ...

Gate-level faults, fault collapsing, and structural modeling in Verilog.

The material is structured into two main parts: developing test environments and implementing testable hardware. Key Topics Covered The book by Zainalabedin Navabi (2010) is a

The text treats testing and testability as integral parts of the digital design process rather than afterthoughts.

Scan architectures, RT-level scan design, and Boundary Scan (JTAG). This allows for a mixed hardware/software environment where

Random and deterministic test generation methods, plus sequential circuit test generation.